Reference is made to FIG. 1 which illustrates a block diagram of a simplified communications system 10. The system 10 includes a transmitter (TX) 12 and a receiver (RX) 14. The transmitter 12 and receiver 14 are coupled through an interface 16. The interface 16 comprises a data bus connection 18 adapted to support parallel communication of a plurality of data bits (for example, eight bits of DATA[7:0]) from the transmitter 12 to the receiver 14. The interface 16 further comprises a clock connection 20 adapted to support communication of a clock signal (for example, on a single line, as a clock signal CLK_PAD) from the transmitter 12 to the receiver 14. The transmitter 12 and receiver 14 are typically circuits, such as integrated circuits, mounted to a circuit board (for example, a printed circuit board) 22. The circuit board 22 includes a plurality of electrical traces (not explicitly shown) coupled between the transmitter 12 and receiver 14 which provide the data bus connection 18 and clock connection 20.
The receiver 14 uses the received clock signal on the clock connection 20 to latch the received data bits on the data bus connection 18. For example, the receiver 14 may operate to latch data present on the data bus connection 18 at the leading edge of the received clock signal. Receipt of the clock signal is thus critical to proper operation of the receiver 14.
It is known by those skilled in the art that there is an upper limit to the frequency of the clock signal which can be transmitted over the circuit board 22 and received by the receiver 14. This upper limit will then impose a corresponding upper limit on the rate at which the data bits can be transmitted over the circuit board 22 and received by the receiver 14. For example, the circuit board 22 may not be able to support a clock signal CLK_PAD transmission at a frequency in excess of 100 MHz, and thus the rate of data bit transmission over the data bus connection 18 may be limited to about 50 MHz.
There is a need in the art to address the clock frequency upper limit issue noted above in connection with supporting the interfacing of a transmitter circuit and a receiver circuit, and more specifically to support DATA transmission over the data bus connection 18 at rates approaching the upper limit for the circuit board 22.